A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks

The IEEE 1687 standard introduces several novelties, most notably Reconfigurable Scan Networks (RSNs), i.e., scan chains whose length can change dynamically. These architectures offer important advantages but can result in extremely complex integrity test following traditional structural approaches. In this paper, we will present an innovative approach to RSN test and debug based on the functional features of the standard, which is able to greatly speed up test generation time while guaranteeing a precise fault coverage

Towards a Secure and Reliable System

Abstract. In this article we describe a system based on a 32-bit processor, Leon, complete with security features offered by a specific cryptographic AES IP. Hardening is done not only on the principal hardware components but on the operating system as well, with attention for possible interaction between the different levels. The cryptographic IP is protected too to offer good resistance against, for example, fault-based attacks

Approximate computing design exploration through data lifetime metrics

When designing an approximate computing system, the selection of the resources to modify is key. It is important that the error introduced in the system remains reasonable, but the size of the design exploration space can make this extremely difficult. In this paper, we propose to exploit a new metric for this selection: data lifetime. The concept comes from the field of reliability, where it can guide selective hardening: the more often a resource handles "live" data, the more critical it be-comes, the more important it will be to protect it. In this paper, we propose to use this same metric in a new way: identify the less critical resources as approximation targets in order to minimize the impact on the global system behavior and there-fore decrease the impact of approximation while increasing gains on other criteria

New Perspectives on Core In-field Path Delay Test

Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains, widely supported by commercial tools. However, functional testing may be a desirable choice in this context because it allows to catch faults at-speed with no hardware overhead and it can be used both for endof-manufacturing tests and for in-field test. The purpose of this article is to compare the results that can be achieved with both approaches. This work is based on an open-source RISC-V-based processor core as benchmark device. Gathered results show that there is no correlation between stuck-at and path delay fault coverage, and provide guidelines for developing more effective functional test

Evolution-guided Engineering of Alpha/Beta Hydrolases

University of Minnesota Ph.D. dissertation. June 2017. Major: Biochemistry, Molecular Bio, and Biophysics. Advisor: Romas Kazlauskas. 1 computer file (PDF); xx, 321 pages.This work applies principles from evolution to engineering enzyme properties. Specifically, by examining the phylogeny and evolved sequence diversity in a group of α/β-hydrolase fold enzymes from plants, we are able to engineer proteins with broader chemoselectivity, altered enantioselectivity, and increased stability. A number of ancestral α/β-hydrolases fold proteins were reconstructed in one set of experiments. These were more likely than related modern proteins to have relaxed chemoselectivities and, in one case, was more useful for synthesizing medicinally important molecules. Relative to modern enzymes, ancestral enzymes near functional branch points could catalyze more esterase and hydroxynitrile lyase reactions, as well as a number of other types of reactions: decarboxylation, Michael addition, γ-lactam hydrolysis, and 1,5-diketone hydrolysis. This finding helps to demonstrate the important role that enzyme promiscuity plays in the evolution of new enzymes. Additional experiments and structural analysis on one of these reconstructed ancestral enzymes, the early hydroxynitrile lyase HNL1 found that it is both more thermostable and more promiscuous than its modern relatives, HbHNL and MeHNL. X-ray crystallographic studies revealed, counterintuitively, that larger amino acids in the active site of the ancestor actually increased the size of the substrate binding pocket relative to modern relatives. To take advantage of the promiscuity observed in HNL1, it was used in the asymmetric synthesis of a precursor for the important pharmaceutical propranolol. Another set of experiments altered enantioselectivity by making phylogenetically informed mutations. The active sites from two related hydroxynitrile lyases, HbHNL and AtHNL, were modified to resemble their last common ancestor. This resulted in altered enantioselectivity, and in the case of AtHNL, reversed enantioselectivity. Surprisingly modeling suggested that some of these mutants use a previously undescribed mechanism. This may have been the extinct ancestral mechanism that served as an evolutionary stepping stone that allowed descendant lineages to diverge to either the S-HNL mechanism used by HbHNL, or the R-HNL mechanism used by AtHNL. A final set of experiments used a variety of methods to identify stabilizing mutations in another plant α/β-hydrolase, SABP2. All of the methods were able to identify stabilizing mutations. The most stabilizing mutations were identified by methods that used no structural information. Random mutagenesis identified highly stabilizing mutations, but required screening thousands of mutants. The most efficient approaches were found to be those that used sequence information from either one stable homolog, or the consensus of many homologs, to identify potential stabilizing mutations. Residues that evolution has conserved are often important for stabilizing a protein. We created a software application, Consensus Finder, to automate the process of identifying stabilizing mutations by consensus

Proof of concept study on coronary microvascular function in low flow low gradient aortic stenosis

ObjectivesWe hypothesised that low flow low gradient aortic stenosis (LFLGAS) is associated with more severe coronary microvascular dysfunction (CMD) compared with normal-flow high-gradient aortic stenosis (NFHGAS) and that CMD is related to reduced cardiac performance. MethodsInvasive CMD assessment was performed in 41 consecutive patients with isolated severe aortic stenosis with unobstructed coronary arteries undergoing transcatheter aortic valve implantation (TAVI). The index of microcirculatory resistance (IMR), resistive reserve ratio (RRR) and coronary flow reserve (CFR) were measured in the left anterior descending artery before and after TAVI. Speckle tracking echocardiography was performed to assess cardiac function at baseline and repeated at 6 months. ResultsIMR was significantly higher in patients with LFLGAS compared with patients with NFHGAS (24.1 (14.6 to 39.1) vs 12.8 (8.6 to 19.2), p=0.002), while RRR was significantly lower (1.4 (1.1 to 2.1) vs 2.6 (1.5 to 3.3), p=0.020). No significant differences were observed in CFR between the two groups. High IMR was associated with low stroke volume index, low cardiac output and reduced peak atrial longitudinal strain (PALS). TAVI determined no significant variation in microvascular function (IMR: 16.0 (10.4 to 26.1) vs 16.6 (10.2 to 25.6), p=0.403) and in PALS (15.9 (9.9 to 26.5) vs 20.1 (12.3 to 26.7), p=0.222). Conversely, left ventricular (LV) global longitudinal strain increased after TAVI (-13.2 (8.4 to 16.6) vs -15.1 (9.4 to 17.8), p=0.047). In LFLGAS, LV systolic function recovered after TAVI in patients with preserved microvascular function but not in patients with CMD. ConclusionsCMD is more severe in patients with LFLGAS compared with NFHGAS and is associated with low-flow state, left atrial dysfunction and reduced cardiac performance

Integrated circuit test apparatus and method

Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.</p

System Level Coordination of Multiple-Standard DfT

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Conception d'un Système Embarque Sur et Sécurisé

This PhD researches a global methodology enabling to improve the dependability and security level against transient logic faults (natural or provoked) appearing inside a hardware/software integrated system, like for instance a smart card. Results can be applied to all systems built around a synthesisable microprocessor core and a set of specialised peripherals. The protection methods operate simultaneously and in complementary manner on hardware, application software and interface layers (most noticeably, the operating system). High level modifications have been favoured for their advantages in terms of generality, configurability, portability and perpetuity. The proposed approach aims at achieving a good trade-off between robustness and overheads, from both hardware and performance point of views. It is applied on a significant system example, representative of an embedded monoprocessor system, based on the 32-bit Leon2 processor and the eCos operating system. The processor has been modified to improve his ability to react against perturbations, by modifying its cache memories, their controllers and the integer unit pipeline. The operating system has been modified as well to implement a recovery technique based on the reutilisation of existing functions, noticeably the context switch function, in collaboration with the detection techniques applied at hardware level. A demonstrator executing representative cryptographic and image processing applications has been developed and targeted by fault injection experiments.Cette thèse s'attache à définir une méthodologie globale permettant d'augmenter le niveau de sûreté et de sécurité face à des fautes logiques transitoires (naturelles ou intentionnelles) survenant dans un système intégré matériel/logiciel, de type carte à puce. Les résultats peuvent être appliqués à tout circuit construit autour d'un cœur de microprocesseur synthétisable et d'un ensemble de périphériques spécialisés. Les méthodes de protection portent simultanément, sur le matériel, le logiciel d'application et les couches d'interface (en particulier, le système d'exploitation). Les modifications sur des descriptions de haut niveau on été privilégiées pour leurs avantages en terme de généralité, configurabilité, portabilité et pérennité. L'approche proposée vise un bon compromis entre le niveau de robustesse atteint et les coûts induits, aussi bien au niveau matériel qu'au niveau performances. Elle est appliquée et validée sur un système significatif, représentatif d'un système embarqué monoprocesseur

Accessing 1687 systems using arbitrary protocols

International audienceThe IEEE 1687 standard enabled the possibility of “alternate access methods” beyond the 1149.1 Test Access Port but did not define how these protocols could be integrated into the 1687 network. In this paper, we propose a solution that is able to support access to the 1687 capabilities through any generic interface